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Question1) The range of representable normalized numbers in the floating point binary fractional representation in a 32-bit word with 1-bit sign, 8-bit excess 128 biased exponent and 23-bit mantissa is

Option- ['2-128 to (1 – 2-23 ) × 2127', '(1 – 2 –23 ) × 2 –127 to 2128', '(1 – 2 –23 ) × 2 –127 to 2 23', '2 –129 to (1 – 2 –23 ) × 2 127']

Answer: 2 –129 to (1 – 2 –23 ) × 2 127

Explaination: 2 –129 to (1 – 2 –23 ) × 2 127

Question2) Given √224r = 13r the value of radix r is

Option- ['10', '8', '6', '5']

Explaination: 5

Question3) The hexadecimal equivalent of the binary integer number 110101101 is:

Question4) Perform the following operation for the binary equivalent of the decimal numbers (−14)10+(−15)10 The solution in 8 bit representation is:

Option- ['11100011', '00011101', '10011101', '11110011']

Explaination: 11100011

Question5) Consider three registers R1, R2, and R3 that store numbers in IEEE−754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively. If R3 = R1 / R2, what is the value stored in R3 ?

Option- ['0x40800000', '0xC0800000', '0x83400000', '0xC8500000']

Explaination: 0xC0800000

Question6) Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?

Option- ['15', '21', 'D2', '528']

Explaination: 15

Question7) Consider the following representation of a number in IEEE 754 single-precision floating point format with a bias of 127.

S : 1 E : 10000001 F : 11110000000000000000000

Here, S,E and F denote the sign, exponent, and fraction components of the floating point representation. The decimal value corresponding to the above representation (rounded to 2 decimal places) is ____________.

Option- ['-7.75', '+7.75', '-5.57', '5.75']

Explaination: -7.75

Question8) Which of the following addressing modes are suitable for program relocation at run time ?

Option- ['(i) and (iv)', '(i) and (ii)', '(ii) and (iii)', '(i), (ii) and (iv)']

Explaination: (ii) and (iii)

Question9) Direction for questions 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

Instruction Operation Instruction Size(in words)

MOV R1,5000; R1 ¬ Memory 2

MOV R2, (R1); R2 ¬ Memory[(R1)] 1

ADD R2, R3; R2 ¬ R2 + R3 1

MOV 6000, R2; Memory  ¬ R2 2

HALT Machine halts 1

Consider that the memory is byte addressable with size 32 bits, and the program has been loaded starting from memory location 1000 (decimal). If an interrupt occurs while the CPU has been halted after executing the HALT instruction, the return address (in decimal) saved in the stack will be

Option- ['1007', '1020', '1024', '1028']

Explaination: 1028

Question10) Directions for question 63 to 64: Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3.

Instruction Operation Instruction Size(in words)

MOV R1,5000; R1 ¬ Memory 2

MOV R2, (R1); R2 ¬ Memory[(R1)] 1

ADD R2, R3; R2 ¬ R2 + R3 1

MOV 6000, R2; Memory  ¬ R2 2

HALT Machine halts 1

Let the clock cycles required for various operations be as follows: Register to/ from memory transfer: 3 clock cycles ADD with both operands in register : 1 clock cycle Instruction fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is

Option- ['29', '24', '23', '20']

Explaination: 24 